This invention relates to methods of forming storage capacitors in integrated circuitry memory cells and related integrated circuitry.
As integrated circuitry memory cells become increasingly smaller, it becomes more difficult to realize desired memory cells which have enough cell capacitance to store information for a reasonable amount of time. The industry has approached the challenge of providing cell capacitance from two different directions.
According to a first direction, storage capacitors are fabricated over a semiconductor wafer. Such capacitors, known as container capacitors, are typically formed by etching into an insulating layer which is formed over a wafer outer surface. One disadvantage of this is approach is that as the memory cells continue to decrease in size, the capacitors have to become narrower and taller in construction in order to maintain a desirable capacitance. Accordingly, the topology of the wafer becomes worse from the standpoint of its impact on several processing steps such as lithography, etching, and mechanical substrate abrading such as chemical mechanical polishing.
According to a second direction, trenches are etched into a substrate and capacitors are formed within the trenches. Such capacitors are known as trench capacitors. A major disadvantage of this approach is that very deep, high aspect ratio trenches must be etched into the substrate. Additionally, complicated strapping mechanisms must be employed to ground the cell.
This invention grew out of concerns associated with increasing cell capacitance while reducing topography and strapping requirements.
Methods of forming capacitors and related integrated circuitry are described. In a preferred embodiment, the capacitors form part of a dynamic random access memory (DRAM) cell. According to one aspect of the invention, a first insulating layer is formed over a semiconductive material layer. A conductive gate is formed over the semiconductive material layer. A second insulating layer is formed over the gate and thereafter etched to form a capacitor container. In one implementation, such etch is conducted to outwardly expose the semiconductive material layer. In another implementation, such etch continues into the semiconductive material layer. In yet another implementation, such etch is conducted completely through the semiconductive material layer and into the first insulating layer.
In a preferred implementation, a storage capacitor is formed within the capacitor container which extends both elevationally above and elevationally below the gate. According to another aspect of the invention, adjacent word lines are formed over the first insulating layer and source/drain diffusion regions are formed within the semiconductive material laterally outward of the word lines. Respective capacitor containers are etched into the diffusion regions and capacitors are formed within the etched containers. In a preferred implementation, storage node material which constitutes part of the capacitors is in electrical contact with the respective diffusion regions and comprises part of a DRAM cell.